Tiempo AS (Grenoble, France) has said it will demonstrate the first synthesis tool for asynchronous logic that operates from standard design languages at the design automation conference, due to be held July 27 to 30 in San Francisco.
The tool is called Asynchronous Circuit Compiler, or ACC, and it generates asynchronous and delayinsensitive circuits from a model written in a standard hardware description language. ACC takes as input a description written in SystemVerilog (IEEE Standard 1800-2005) as a Transaction-Level Model (TLM) and generates a gate-level netlist in standard Verilog format.